SystemVerilog Assertion - Terminology Check on Assert/Deassert

Hello Sangwoo,

Your confusion is understandable. During that book you see they have use this notation in many places.
Here “FRAME” is a negative logic signal. When FRAME goes low (1->0) it actually considered as “Asserted” (where FRAME 0->1 if it’s a positive logic signal).
By default we mean any signal as “positive logic” signal. Here in this book it’s all considered negative logic signals.

But your understanding of Assertion, de-assertion are correct.

Hope this helps.

Kranthi