SystemVerilog Assertion - Terminology Check on Assert/Deassert

SystemVerilog
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Hi all,

Just wanted to clarify the terminology on asserting and deasserting.

I understand that asserting a signal means you make that signal active, and deasserting means deactive that signal.

I understood asserting a signal as making that signal go from a low to a high (0 to 1), and that deasserting would do the opposite.

I came across this example and the following example under the screenshot I will be providing below.

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The question that I wanted to ask is that how is it that one would use ‘assert’ on a signal with $fell function on it as the parameter? I am slightly confused on how assert is used for signals that goes Low, and deassert for signal that goes high in the context of the screnshot examples that I have provided.

Thank you,

Sangwoo.

2

Hello Sangwoo,

Your confusion is understandable. During that book you see they have use this notation in many places.
Here “FRAME” is a negative logic signal. When FRAME goes low (1->0) it actually considered as “Asserted” (where FRAME 0->1 if it’s a positive logic signal).
By default we mean any signal as “positive logic” signal. Here in this book it’s all considered negative logic signals.

But your understanding of Assertion, de-assertion are correct.

Hope this helps.

Kranthi

3

Note that the signal name is FRAME_ which FRAME followed by _. You can read that as FRAME-BAR. That notation is used to indicate the signal is active low, or the complement of FRAME active high. Other notations used to indicate active low signals are FRAMEn, FRAME_n, or FRAME_B.