I"m new to using assertions and I was going through some best practices paper from a website. The below assertion compiles fine. always @* begin ERR_reset_went_unknown: assert(!$isunknown(Reset)) else begin $error("ERR_reset_went_unknown"); repeat(2) @(posedge Clock); $f…

In reply to markylew : All assertions labels must be unique. Also, watch the syntax and the use of the end of statement “:”. [image] EDA Playground Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser. module m;…

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markylew August 14, 2020, 9:43pm 3

In reply to ben@SystemVerilog.us:

Thanks Ben!