SystemVerilog Assertion label

SystemVerilog
,
2

In reply to markylew:
All assertions labels must be unique.
Also, watch the syntax and the use of the end of statement “:”.


module m; 
   bit Reset, clock; 
   always @* begin
    ERR_reset_went_unknown: assert(!$isunknown(Reset))
    else  $error("ERR_reset_went_unknown");  
   end
  
  always @* begin
    ERR_reset_went_unknown2: assert(!$isunknown(Reset));
    // else  $error("ERR_reset_went_unknown");  
   end
  
  always @* begin //The always @* trigger will also catch the 0-to-X/Z-to-1 transitions
    ERR_reset_went_unknown3: assert(!$isunknown(Reset));
    
    assert(!$isunknown(Reset));
  end
  
  initial begin 
      repeat(2) @(posedge clock);
      $finish;
  end
  
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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