Systemverilog assertion for checking signal width

SystemVerilog
,
1

Hi,

I am pretty new to systemverilog assertions.
I want to write assertion for checking signal width.

Can anybody please help with an small example of that?

Thanks,
Ashish

2

In reply to ashisha_arm:

Assertions are mostly used for creating dynamic checks.(To verify protocol violation, data correctness…)

Maybe immediate assert might work for you but i am not sure whether there is anyway to get the width of a signal.
In your procedural code you can add following code.


assert(expected_width == actual_width) $display("Width is same");
else $fatal("Signal width mismatch");

For timing related checks $width system task can be used.(this checks for pulse width). I think you are not looking for this.

3

I want to write assertion for checking signal width.

You could use the signal edges as the trigger for the assertion, and $realtime to capture time.
On the comparisons of time, getting an exact time measure (e.g., width ==30.0 exactly) is problematic because of the resolutions. However, you can use a range. In the example below, I assume a width >29.0 and <= 30.

module test_time;
// I want to write assertion for checking signal width.
	bit s; 
	property p_rise_sigwidth; 
		realtime v_t, v_now; 
		@ (posedge s) (1, v_t=$realtime) |-> @(negedge s) 
			 (1, v_now=$realtime - v_t) ##0 
			 (v_now <= 30.0) && (v_now > 29.0); 
	endproperty : p_rise_sigwidth
	
	ap_rise_sigwidth:  assert property (p_rise_sigwidth); //

endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
4

Hi,

The above code is fine to check only once. If the bit is toggling continuously to some extent, so now I want to find pulse width for every toogle, How its done?

5

In reply to janudeep3:

The above code is fine to check only once. If the bit is toggling continuously to some extent, so now I want to find pulse width for every toogle, How its done?

Why to you say “only once”? There is a new attempt for this assertion at every @ (posedge s)
If you want only once, then put the assertion inside an initial statement.
Ben SystemVerilog.us

6

Suppose for example COnsider the following example

"a" and "b" are two signals which are of one bit and they are of logic type with "x" as initial value. 
At time t1, a becomes 1,
At time t2, b becomes 0,
At time t3, b becomes 1,
At time t4, b becomes 0,
At time t5, b becomes 1,
At time t6, b becomes 0,
At time t7, b becomes x.

For this code, How to find pulse width of ‘b’ signal. I even dont know when b becomes x and also b is dependent on a. Till b reaches x, I should be able to find the High pulse width of b and also the low pulse width of b?

Did you get my question Ben?