System verilog syntax

SystemVerilog
1

Can anyone explain to me the following syntax?

array_1={<<{33'h000000023}};
2

{<<{expression}}

is the SystemVerilog streaming operator which in this case is unpacking the literal 'h23 in reverse order (right LSB to left MSB) into the unpacked array_1 (assuming it is declared as an unpacked array).

3

In reply to dave_59:

Thanks Dave!

Is there a way to concatenate the “expression”. As an example I want to do the following:

bits= 1001010 // These are 7 bits only
array_1 ={<<{33'b {bits}}} // I want 33 bits here with 0 appending after 7 bits. In this case the following number '000000000000000000000000001001010'

I tried the above but got the error:

unexpected character’{’ is illegal in this context.

4

In reply to debuggerzc:

You could do

array_1 ={<<{26’b0,bits}}};

But if you give me the declaration of array_1, there might be a better way because the streaming operator will 0 fill on the right automatically if the target is has more bits than the source. It would also help to show us the final result you are looking for.