System Verilog Constraints

SystemVerilog
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1

1.How to write constraint to generate even number,odd number and prime number in an array.array consists of 100 locations.Generated numbers should not repeat ?
rand int array[100];

array[0] = 4;
array[1] = 5;
array[2] = 3;
like this we have to fill in all locations.

2

In reply to SIVANAGENDRAREDDY:

An array constrained to have any even or odd number is the same has having no constraint at all.

3

In reply to SIVANAGENDRAREDDY:

You can use some thing like this:

For odd number:

constraint c_odd_num {

     foreach array[i]{
      array[i] % 2 != 0;
      if(i >0){
       array[i] > array[i-1];
      }
    }
   }

For even number:

constraint c_even_num {
     foreach array[i] {
      array[i] %2 == 0;
    }
    if(i >0){
       array[i] > array[i-1];
      }
   }

For Prime number:

 constraint c_prime_num {
       foreach array[i] {
        array[i] %2 != 0;
        array[i] %3 != 0;
        array[i] %5 != 0;
       } 
      if(i >0){
       array[i] > array[i-1];
      }
     }