In reply to ben@SystemVerilog.us:
This is exactly what I was suspecting. The expectation is to get gnt signal each time the req signal is high. Can you suggest me what updates will required to catch the issue in the following scenario:
req 0 1 0 1 0 0 0 0 0 0 0
gnt 0 0 0 0 0 0 0 1 0 0 0
With the below assertion, this issue will not get caught, right?
assert property (@(posedge clock)
req |-> ##[4:32] gnt);