System Verilog Concurrent Assertions

SystemVerilog
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4

In reply to fenil_shah: At every cycle req==0 the assertion fails.

req 0 1 1 0 0 0 0 0 0 0
gnt 0 0 0 0 0 0 1 0 0
Th1   <---------> PASS ##5
Th2.     <----++> PASS ##4.

You need vacuity

assert property (@(posedge clock) 
              req |-> ##[4:32] gnt);