In reply to ben@SystemVerilog.us:
In reply to mahe424:
// Option 2
property exp;
@(posedge clk) disable iff (~resetn)
($rose(a) |-> ##[1:10] $rose (b)) #-# always (c !== 1’b1);
endproperty
a_exp : assert property (exp) else $fatal(“error in assertion”);
// The #-# is the followed-by operator.
Thanks Ben. If signal ‘c’ shall not assert only for sometime how to add clock cycles to always?