In reply to UVM_LOVE:
Thank you for your interest in SystemVerilog directed tests. It’s a fundamental skill for working with hardware design and verification. If you’re not familiar with writing simple directed tests in SystemVerilog, I encourage you to explore online resources and tutorials to enhance your understanding. There are many helpful guides available that can provide step-by-step instructions. Developing a strong foundation in this area will greatly benefit your work in the field. Best of luck with your learning journey!
After that, you should start studying constrained-random-tests (CRT), but this is another story.
Ben