System verilog assertion

SystemVerilog
3

In reply to ben@SystemVerilog.us:

If you want to test an assert statement about option 2.

// Option 2
property exp;
   @(posedge clk) disable iff (~resetn)
     ($rose(a) |-> ##[1:10] $rose (b)) #-# always (c !== 1'b1);
  endproperty
  a_exp : assert property (exp) else $fatal("error in assertion");
// The #-# is the followed-by operator.

What approach is proper for you? I want to learn from it.