System verilog assertion

SystemVerilog
2

In reply to mahe424:

Requirements:

  • ‘a’ asserts and then after 10 clock cycles signal’b’ assets to 1
  • Once signal ‘b’ asserts after 10 clock cycles signal ‘c’ shall always be 0

// Option 1
property exp;
   @(posedge clk) disable iff (~resetn)
    first_match($rose(a) ##[1:10] $rose (b))|-> always (c !== 1'b1);
  endproperty
  a_exp : assert property (exp) else $fatal("error in assertion");

// Option 2
property exp;
   @(posedge clk) disable iff (~resetn)
     ($rose(a) |-> ##[1:10] $rose (b)) #-# always (c !== 1'b1);
  endproperty
  a_exp : assert property (exp) else $fatal("error in assertion");
// The #-# is the followed-by operator. 

// Option 3, without first_match, which is strongly disliked by my colleague) 
property exp;
   @(posedge clk) disable iff (~resetn)
    ($rose(a) ##[1:10] $rose (b)) intersect b[->1] |-> always (c !== 1'b1);
  endproperty
  a_exp : assert property (exp) else $fatal("error in assertion");

Ben Cohen
Ben@systemverilog.us
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Getting started with verification with SystemVerilog