System verilog assertion to check clock switch and period

SystemVerilog
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1

I’m working on a project. I need to verify a clock management unit. This unit’s function includes different clock source switch, clock divide, clock on/off control.
I’m new on SVA.
I want to know a solution with SVA:

  1. Check clock on/off
  2. Check clock switch
  3. Check clock divide

Thanks a lot.

2

In reply to Kevinwu:

Before you can write any SVA, you need to get these requirements into a form that explains what it means to pass, and what would cause a failure,

3

In reply to dave_59:

Thanks.
For 1:
assume “en_clk” is clock enable.
PASS: en_clk=1,clock toggle.
or en_clk=0,clock stop.
Fail: en_clk=1,clock stop.
en_clk=0,clock toggle.

For 2:
assume “cksel[1:0]” is select signal to choose which clock is system clock
PASS: cksel[1:0]=2’b00, sys_clk=clk1
cksel[1:0]=2’b01, sys_clk=clk2
cksel[1:0]=2’b10, sys_clk=clk3
cksel[1:0]=2’b11, sys_clk=clk4
FAIL: not operate as above.

For 3:
assume “div[1:0]” is clock divide scale.
PASS: div[1:0]=2’b00, sys_clk_div=sys_clk
div[1:0]=2’b01, sys_clk_div=sys_clk/2
div[1:0]=2’b10, sys_clk_div=sys_clk/4
div[1:0]=2’b11, sys_clk_div=sys_clk/8
FAIL: not as above
My issue is how to present above check with SVA.

4

Anybody help?
My project is urgent. Thanks for your help in advance.