System verilog assertion on asynchronous signal that kept calibrated

SystemVerilog
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3

In reply to ben@SystemVerilog.us:
Another suggestion:


// Suppose that we create two properties. Also assume that the shift 
// between source and target is such that there is no all 0 gap, i.e., there is overlap.
  property p1;
      realtime source_t;
      realtime target_t;
      @(posedge source)  // source is first
        (!target, source_t=$realtime, $display("**** Start **** \nsource_t=%0t",source_t)) ##0
      @(posedge target) (1, target_t=$realtime, $display("target_t=%0t",target_t)) |->
      (target_t - source_t) <= calibration_value; //Should be a bound, not exct value
    endproperty

  property p2;
       realtime source_t;
      realtime target_t;
      @(posedge target) 
        (!source, target_t=$realtime, $display("**** Start **** \ntarget_t=%0t",target_t)) ##0
      @(posedge source_t) (1, source_t=$realtime, $display("source_t=%0t",source_t)) |->
      (source_t -target_t) <= calibration_value;
    endproperty

assert_property(p1 and p2) ; // or as two separate assertions.

// Would that work? If there is no overlap to start with, we could perhaps try something 
// with killing one property if the other one completes. not sure.