System Verilog assertion for accessing a register

SystemVerilog
1

I am new to system verilog assertions. I am trying to write an assertion for the following requirement.

Requirement : The register r1 can be accessed only if register r2 has a value of 1.

I don’t know how to write an assertion for accessing a register.
Thank you.

2

In reply to rahulk:

// a register is a variable with a range (e.g., of type logic[7:0]. 
logic[7:0] r1, r2; 
logic r1_enb; // r1 enable 
let t=8'b"00001111"; 
//  r1 can be accessed only if register r2 has a value of 1.
// If requirements states that if the sampled value of r2==t then r1_enb==1 at the next cycle 
a_reg: assert property(@ (posedge clk) r2==t |=> r1_enb );  

// You can also write an immediate assertion than when r2==t, r1_enb==1
 always_comb a1: assert final(r2==t && r1_enb);

Get a book to study SVA.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

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3

In reply to ben@SystemVerilog.us:

Thanks