In reply to rahulk:
// a register is a variable with a range (e.g., of type logic[7:0].
logic[7:0] r1, r2;
logic r1_enb; // r1 enable
let t=8'b"00001111";
// r1 can be accessed only if register r2 has a value of 1.
// If requirements states that if the sampled value of r2==t then r1_enb==1 at the next cycle
a_reg: assert property(@ (posedge clk) r2==t |=> r1_enb );
// You can also write an immediate assertion than when r2==t, r1_enb==1
always_comb a1: assert final(r2==t && r1_enb);
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Ben Cohen
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy