Synchronizing C code (DPI-C) and Systemverilog code for purpose of sequencer timing, etc

SystemVerilog
1

Are there established methods of “allowing” C code to monitor simulation (simulated) time, so that the C code could perform function(s) based on simulation time? Basically to get SV’s $time accessible to C code. I think it’s possible to pass $time to the C code on every DPCI-C function call, but that’s not pretty. Are there ways for the C code to access (get, and perhaps even set) SV variables?

Note that although (I think) DPI-C C code is meant to be primarily invoked from SV code, the C code here is running in pthread(s), so the execution order of the Questa simulation (engine) and the C code is not quite clear to me (yet). I will likely have follow-on questions (or do more experiments myself) to get more clarity on these kind of things.

My current need for greater SV-to-C communication/interaction is to improve the way C code can throttle sequencer data, although these mechanisms will be useful for lots of other testbench functionality.

Thank you in advance for any help.

2

In reply to plu:

A Hardware Description Languages (HDL) is designed to model a massive amount of concurrent hardware processes or “threads” simulating on a machine with a limited or single CPU thread. The simulation kernel makes sure all simulated processes share the global concept of (simulated) time.

SystemVerilog’s DPI allows you to go back and forth into C, but it uses the simulation kernel to keep simulation time synchronized. So you can use the DPI to get and set variables in SystemVerilog, including getting the current time.

But a CPU’s operation system “thread” is different from a CPU’s operation system “thread” and the only time it know about comes from a real-time clock.

You might want to read: Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI | DVCon 2013 | Verification Academy