In reply to SparkyNZ:
I’ve done some more reading on blocking vs non-blocking assignments and I’m confused even more. The use of language seems contradictory to me:
always @(posedge i_clock)
begin
r_Test_1 <= 1'b1;
r_Test_2 <= r_Test_1;
r_Test_3 <= r_Test_2;
end
The always block in the Verilog code above uses the Nonblocking Assignment, which means that it will take 3 clock cycles for the value 1 to propagate from r_Test_1 to r_Test_3.
OK, that’s a new concept for me to grasp but I can - at least where there are no if() statements involved. It’s defining a chain and value propagation is linked to i_clock cycles.
*Now consider this code:
*
always @(posedge i_clock)
begin
r_Test_1 = 1'b1;
r_Test_2 = r_Test_1;
r_Test_3 = r_Test_2;
end
*See the difference? In the always block above, the Blocking Assignment is used. In this example, the value 1 will immediately propagate to r_Test_3. The Blocking assignment immediately takes the value in the right-hand-side and assigns it to the left hand side. Here’s a good rule of thumb for Verilog:
In Verilog, if you want to create sequential logic use a clocked always block with Nonblocking assignments.*"
That last sentence confuses me completely. “Sequential logic” to me suggests steps - things (assignments) that happen in sequence. But what does “sequential logic” really mean in this context? Does “sequential” really mean “logic associated with a clock” rather than “logic evaluation in the order of Verilog statements” ?
So… when I read “sequential logic” (and use of non-blocking assignments), should I be trying to think of how a value will propagate every clock cycle rather than thinking about the ordering of the lines of code?
I read that the last non-blocking assignment will always be the one which is evaluated in a clock cycle. OK.
So do if() statements really affect non-blocking assignments in a different way to a blocking assignment? I guess not… unless a sequence of if() statements are provided:
if( flag )
val <= val + 1'b1;
if( val % 2 == 0 )
val <= val + 1'b3;
What would happen here? if flag is true and (val % 2) is 0, does that mean that only the val <= val + 1’b3 statement would be take effect in this clock cycle? (ie. the val <= val + 1’b1 statement is irrelevant in this case?