Synchronization: Setting and Clearing a Value using Different Clocks/Processes

In reply to Mark Curry:

Thanks Mark. Fundamentally, I think I know where you’re coming from. :-) Yes, my baud clock is generated from the master clk so I can see what you’re suggesting on principle - ie - the baudTick will either rise or fall on one of the clk transitions. I will have try and get my head around this.

I get that the <= operators are non-blocking but I’m still very grey about the actual assignment behaviour (more learning I’m going to have to research). For example, I get how an assign statement asynchronously works… but when the non-blocking assignments appear within and before conditions, I have to question this behaviour:

counter <= counter + 1'b1;   // non-blocking!! 
  if( counter > 50000000 ) // 1Hz
    counter <= counter + 2'b1;

For example, in the code snippet above, the 2 counter assignments would still occur in sequence wouldn’t they?

Some of the CDC stuff I was reading earlier this morning was far too much to digest. However, you have given me a new sense of hope in that I may be able to avoid cross-domain concerns for now. I honestly thought I was going to have to follow something like this:

https://www.fpga4fun.com/CrossClockDomain3.html