Synchronization: Setting and Clearing a Value using Different Clocks/Processes

SystemVerilog
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2

In reply to SparkyNZ:

Welcome to FPGA design. You want everything synchronous to the one clk. (Ask why perhaps in another thread/somewhere else).

Since “baudTick” is (one assumes) generated from clk, you can make a (synchronous) falling edge detector.


bit baudTick_d;
always @( posedge clk )
  baudTick_d <= baudTick;  // Note change all your assignments to non-blocking in your clocked procedural block!

wire fall_baudTick = baud_Tick_d & ~baudTick;

Now use your new falling edge detector synchronously, in the same procedural block:

always_ff @( posedge clk )
begin
  if( fall_baudTick )
    addStringToQueue <= 0;
  
  counter <= counter + 1'b1;   // non-blocking!! 
  if( counter > 50000000 ) // 1Hz
  //...
end

Note: Also consider your requirements of your comparison for 1 Hz. If you can change your comparitor to a power of 2, you’re implementation will be quite a bit smaller.