In reply to ben@SystemVerilog.us:
HI ben , I want to write an assertion for a signal “a” and “b” where the signal “a” is the exact replica of signal “b” just one cycle before.
I am implementing this : -
$rose(a) |-> $past(b,1);
Also it is to be noted that the width of both signals are exactly the same.
Correct me If I am wrong here , because I think this sequence is not checking the width of both signals rather ,only posedges of signals with a cycle of one delay.