In reply to sraja:
Am not clear as to what you mean by “the assertion should not trigger if the past [0 to 2] clock cycles value is din == 00.” If I call “a” what I am looking looking for, and that any sequence of 1, 2, or 3 occurrences of (din ==2’b00) means a result of “!a” then you can express it as follows:
//the assertion should not trigger if the past [0 to 2] clock cycles value is din == 00.
ap_din_a: assert property((din ==2'b00) [*1:3] |-> !a);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
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