SVA to check whether a signal is stable between 2 events

SystemVerilog
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2

In reply to nsiddams:
xyz is stable between the fall of signal ‘reset’ and the rise of signal ‘enable’.


// from fall of reset, XYZ is stable continuously  until and with rose of enable
property stable_check(xyz);
   @(posedge clk) // NO on "disable iff (enable):
   $fell(reset) |-> $stable(xyz) s_until_with $rose(enable);
endproperty



// from fall of reset, XYZ is stable at any time  until, but not 
// necessarily with rose of enable
property stable_check(xyz);
   @(posedge clk) // NO on "disable iff (enable):
   $fell(reset) |-> $stable(xyz) within $rose(enable)[->1];
endproperty

Ben Cohen
Ben@systemverilog.us
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