SVA: throughout corner case | sig1 must be stable throughout sig2

SystemVerilog
, ,
9

In reply to ben@SystemVerilog.us:

Thank you for the thorough explanation, Ben. It seems like

ap_until_sig1_stable_throughout_sig2: assert property(@(posedge clk)       
     $rose(sig2) |=> $stable(sig1) until !sig2); // Need the |=> because the until is a property

is what meets my requirements. However, for some reason I am getting a syntax error when trying to use the ‘until’ property. I think it is a tool issue.
Could you share any alternatives for until?

Thanks,
Ankit