In reply to ben@SystemVerilog.us:
Hi
We usually use $stable(signa_name) to see a signal must be stable in from previous clk cycle. How to check that a signal must be stable within clk cycle
In reply to ben@SystemVerilog.us:
Hi
We usually use $stable(signa_name) to see a signal must be stable in from previous clk cycle. How to check that a signal must be stable within clk cycle