your requirements are ambiguous. Are you talking about a fifo?
If I assume that the data from left gets in at valid_left, and data from out with a valid, then I came up with the following:
// There is a BlackBox with one input bus and one output bus.
// There are VALID signals for each of the buses. The block is clocked by CLK.
// How can I check / assert that the sequence of data in the output bus is the
// same as in the input bus? Latency between input and output data may vary
// (actually latency between VALID signals may vary).
module test2;
parameter UPPER = 9;
bit clk, valid_l, valid_r; // valid left, valid right
bit[15:0] data_l, data_r; // data left, data right
// How long is the sequence?
// What is the start of the sequence
property p_dldr;
bit[15:0] v_d;
@(posedge clk) (valid_l, v_d=data_l) |-> ##[1:UPPER] data_r==v_d;
endproperty
a_: assert property ( p_dldr );
initial forever #5 clk=!clk;
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115