In reply to ben@SystemVerilog.us:
Thanks Ben for your help. I agree with intersect solution
//Making sure that bmode is not high for 2 cycles and then when oe and dack are high
endsequence
property pbrule1c;
@(posedge clk) $fell(bmode) |-> (##2 dack==1 && oe==1[*4]) intersect !bmode[*6]; // 6 cycles total
endproperty
Seq 1 intersect seq 2 => two sequences start at the same time and end at the same time. satisfies my condition here .
May I please know if we can write the same without using intersect , that is using [*] only