In reply to ben@SystemVerilog.us:
I agree about ‘strong’ qualifier. Also, there can be usage of ‘s_eventually’ over here.
assert property (@(posedge clk) req |-> s_eventually gnt);
Refer to this PDF for more alternatives.
In reply to ben@SystemVerilog.us:
I agree about ‘strong’ qualifier. Also, there can be usage of ‘s_eventually’ over here.
assert property (@(posedge clk) req |-> s_eventually gnt);
Refer to this PDF for more alternatives.