In reply to ben@SystemVerilog.us:
I see gnt getting asserted on the 4th clock(after req occurs) in the positive duty cycle. I don’t understand why I see Under Evaluation in my waveform.
In reply to ben@SystemVerilog.us:
I see gnt getting asserted on the 4th clock(after req occurs) in the positive duty cycle. I don’t understand why I see Under Evaluation in my waveform.