SVA: Procedural Assertion didn't Turn_ON

SystemVerilog
1

Hi All,
I need help from this code below.

property vcop_clock_normal_operation_assert;
realtime current_time_vco_normal;
@(posedge vcop) disable iff((sva_enable === 1’b0) || (clkgen_ins_ok !==1’b1))
('1,current_time_vco_normal = $realtime) |=> ((($realtime - current_time_vco_normal) >= vco_clock_time_norm_min) && (($realtime - current_time_vco_normal) <= vco_clock_time_norm_max));
endproperty

always @(refclksel)begin
@(posedge refclk_selected);
@(posedge refclk_selected);

assert property (vcop_clock_normal_operation_assert) else $fwrite(FID,“ASSERT FAIL vcop_clock_normal_operation: %m @ %f \n”,$time);
end
cover property(vcop_clock_normal_operation_assert);

I need to triggers property of “vcop_clock_normal_operation_assert”. whenever changes refclksel, skips the two clock cycles of refclk_selected after triggers the “vcop_clock_normal_operation_assert” property.
But, this property dosen’t turn-ON. It’s always turn-Off. while every condition are valid.
I am not understood of this issue. please look at this. Given solution of this or changes in code.

Thanks,
Chandru

2

In reply to CHANDRU_D:
Looks OK. Maybe you have a property disable condition.
To debug, I would need your test code or at least the waveforms.
Ben

3

In reply to ben@SystemVerilog.us:

Hi Ben,
It’s not disabled. I attached waveform response on below link. You can checked out.

Your text to link here…

Your text to link here…

Your text to link here…

Thanks,
Chandru

4

In reply to CHANDRU_D:
Send me the test code