Sva: once req asserted, 1-5 cycles later ack should be asserted

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:
OOPS! Need to correct the counters
Note: if req and ack are both true you get 2 NBA assignments to the same variable with different values; the simulator may accept the last one, and it will not function as intended.
NEW CHANGE:


always @(posedge clk) begin
        if(req && !ack)  req_count <= req_count + 1; // was if(req) ... * 1'b1
        if(ack && !req)  req_count <= req_count - 1; // was if(ack) ... - 1'b1
    end

Updated code at http://systemverilog.us/vf/unique_ack.sv