SVA error Property declaration must end with "endproperty"

SystemVerilog
, , ,
1

I’m getting an error Property declaration must end with “endproperty” in the following property. Help needed!

property addr_incr_p(_vld, _addr);
@(posedge clk) disable iff(!int_rstn)
if($fell(_vld))
(1’b1,addr_incr_func(_addr)) |-> (_addr==($past(_addr)));
else
_vld |=> (1’b1,addr_incr_func(_addr)) |-> (_addr==($past(_addr)+1));
endproperty

assert property (addr_incr_p(vld, addr)) else begin`uvm_error(“GENERIC PROPERTY”,$sformatf("ADDRESS %0h ",addr)) end;

2

In reply to Nimisha Varadkar:
Your error is the “;” in the first consequent

   
property_statement ::=
   property_expr ;
    | case ( expression_or_dist ) property_case_item
           { property_case_item } endcase
    | if ( expression_or_dist ) property_expr // <--- NO ";" at end 
    [ else property_expr ]

// This compiles OK 
property addr_incr_p(_vld, _addr);
      @(posedge clk) disable iff(!int_rstn)
      if($fell(_vld))
        (1'b1,addr_incr_func(_addr)) |-> (_addr==($past(_addr)))
      else
        _vld |=> (1'b1,addr_incr_func(_addr)) |-> (_addr==($past(_addr)+1));
endproperty

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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3

In reply to Nimisha Varadkar:

I’m getting an error Property declaration must end with “endproperty” in the following property. Help needed!
property addr_incr_p(_vld, _addr);
@(posedge clk) disable iff(!int_rstn)
if($fell(_vld))
(1’b1,addr_incr_func(_addr)) |-> (_addr==($past(_addr)));
else
_vld |=> (1’b1,addr_incr_func(_addr)) |-> (_addr==($past(_addr)+1));
endproperty
assert property (addr_incr_p(vld, addr)) else begin`uvm_error(“GENERIC PROPERTY”,$sformatf("ADDRESS %0h ",addr)) end;

It worked without the ; before else part!

4

In reply to ben@SystemVerilog.us:

Thanks Ben!