In reply to ben@SystemVerilog.us:
Thanks ben, i will try to analyse , by the way how did you enable “Assertion thread view” in questa .
Dave : Please let us know how did you uploaded the image ?
In reply to ben@SystemVerilog.us:
Thanks ben, i will try to analyse , by the way how did you enable “Assertion thread view” in questa .
Dave : Please let us know how did you uploaded the image ?