In reply to cool_cake20:
All signals are sampled in the Preponed region (see 1800’2012 4.4 Stratified event scheduler), just before the clocking event. If you do the analysis, you’ll see that it works OK, as expected.
Ben SystemVerilog.us
In reply to cool_cake20:
All signals are sampled in the Preponed region (see 1800’2012 4.4 Stratified event scheduler), just before the clocking event. If you do the analysis, you’ll see that it works OK, as expected.
Ben SystemVerilog.us