SVA : Disable assertion to bypass transition from x --> 0/1

SystemVerilog
,
1

HI,

I have a situation where there is a variable transition from x to 1/0. i.e A transition of value
from X to 0 is not a rising edge and hence the sequence fails.
I want to filter from triggering the assertion.
I want to know how to detect and filter the assertion not to trigger.

-Regards,
-Raja.

2

In reply to sraja:

Have you tried the $isunknown ( expression )?
$isunknown (data);
// true if any bit of the vector is X or Z
// same as $countbits(data,‘X,‘Z)

logic a=X; 
logic b; 
!$isunknown(a) && rose(a) |-> b;

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

Hi Ben,

Yes, I used the same $isunknown(data).I could able to disable the assertion when clock and rst goes from x to initial value.

Here is the picture

Imgur

Thanks for the solution.

I would like to know the transition from X->0 or X->1 and detect it.how can i do that.is there any construct in SVA. Only for the purpose to detect X → 0/1.

-Regards,
-Raja.

4

In reply to sraja:

I would like to know the transition from X->0 or X->1 and detect it.how can i do that.is there any construct in SVA

You can use a function or just the “===” comparator

logic clk=0, a=1'bX;
	default clocking @(posedge clk); endclocking
	initial forever #10 clk=!clk;   
    	initial #203 a=0; 
	ap_1: assert property(##1 $past(a) === 1'bX) $display ("a=X");

My question though, why are you not using type bit, or initialize the objects of type logic to 0 or something that is not an X. Real hardware does initialize to something, 0 or 1, but not an X.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
5

HI Ben,

Nice Idea!!!
I can do it using bit data type as it is two state type.

I cannot use logic and assign initial value.I am probing rtl signals and assigning to reg data type in the assertion modules.

something like this…
assign sec_clk = `RPITP.opidatacluster0.opistrbmodule.opistrbpgunit.opipcspgstrblane.rxclock_top_dig.rxclock_dll_top1.dll_dig.rxclock_dll_acc.ck_acc;

I use this sec_clk variable in the assertion.
so i think cannot initialize some value.

Thanks you.

-Regards,
-Raja.