SVA : Disable assertion to bypass transition from x --> 0/1

SystemVerilog
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3

Hi Ben,

Yes, I used the same $isunknown(data).I could able to disable the assertion when clock and rst goes from x to initial value.

Here is the picture

Imgur

Thanks for the solution.

I would like to know the transition from X->0 or X->1 and detect it.how can i do that.is there any construct in SVA. Only for the purpose to detect X → 0/1.

-Regards,
-Raja.