I have a situation where there is a variable transition from x to 1/0. i.e A transition of value
from X to 0 is not a rising edge and hence the sequence fails.
I want to filter from triggering the assertion.
I want to know how to detect and filter the assertion not to trigger.
Yes, I used the same $isunknown(data).I could able to disable the assertion when clock and rst goes from x to initial value.
Here is the picture
Thanks for the solution.
I would like to know the transition from X->0 or X->1 and detect it.how can i do that.is there any construct in SVA. Only for the purpose to detect X → 0/1.
My question though, why are you not using type bit, or initialize the objects of type logic to 0 or something that is not an X. Real hardware does initialize to something, 0 or 1, but not an X.
Ben Cohen http://www.systemverilog.us/ben@systemverilog.us
SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448