SVA assertion for realtime variables

SystemVerilog
, , ,
6

In reply to sarth21:
It would really help to show a complete example demonstrating your problem and provide the display messages you are seeing.

The following works for me.

`timescale 1ns/1ps
module top;
  
  realtime mc_b = 4440ps;

  bit di_b, indd_b,reset=1;
  
  initial begin
    #1ns
    di_b   <= 1;
    indd_b <= #4440ps 1; //pass
    #10ns
    di_b   <= 0;
    indd_b <= 0;
    #10ns
    di_b   <= 1;
    indd_b <= #4441ps 1; //fail
    #10ns;
  end

  property idel_b;
     realtime ctime;
    disable iff (!reset)
     @(posedge di_b)
     	(1'b1,ctime=$realtime) |=> 
     @(posedge indd_b)
       mc_b == $realtime-ctime;
   endproperty
  
  assert property (idel_b) $info("pass"); else $error("fail");
endmodule