SVA assertion for realtime variables

SystemVerilog
, , ,
3

In reply to sarth21:
Removed the always block and modified the property as below.

property idel_b;
     realtime ctime;
     disable iff (!reset)
     @(posedge di_b)
     	(1'b1,ctime=$realtime) |=> 
     @(posedge indd_b)
      (mc_b == $floor($realtime-ctime));
endproperty