SVA Assertion - address does not change while request is asserted

SystemVerilog
,
1

I have to write an assertion for the functionality that addr does not change (is stable) while req is asserted

Will the following assertion work optimally or is there a better way to write it

assert property (@(posedge clk) req == 1 |=> $stable(addr));

Thanks

2

In reply to verification_engineer_smart:
Depends on your requirements for stable


addr. 0.0.8.8.0
req.  0.0.1.
 req == 1 |=> $stable(addr)
----------
addr. 0.8.8.0
req.  0.0.1.
 req == 1 |-> $stable(addr)

// if 1st cycle is of interest 
  ##1 req == 1 |-> $stable(addr)

Ben Cohen
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