SVA - assert signal rise with its clock - difference between codes

SystemVerilog
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4

In reply to OE93:

Your second code never works because $rose(sig_in[idx]) is always 0. You are using the same signal as the clock event, and its sampled value is always 0 before it rises. The function call in the first code is a convoluted way of avoiding using sampled values.

Without know exactly how your clocks are modelled and how the signals get assigned, or what is particular about the tests that produced false violations, it is difficult to know what might be wrong. I suggest you might try making your code generic in stages rather than replace the macro all at once. For example the event generation can be replace with this

ev[NUM]
for(genvar i=0;i<NUM;i++) 
  always @( posedge src_clk[i])  -> ev[i];

Then replace the function, then the property.

Finally replace the assertion. Do not place it inside an initial block.

if (EN_CLK_DOMAIN_CHECKER) begin
  for (genvar i = 0; i < NUM; i++) begin : assert_loop
         DETECT : assert property (detect(i, sig_in[i], rstn, clk_event_array[i])) else $error("ERROR - WRONG CLOCK DOMAIN - INDEX [%0d]", i);
     end
end