In reply to dave_59:
Hi Dave
Thanks for your response.
I hope I understood your request-
Of course, due to information security I cannot provide detailed information, but I can explain the motivation:
My concern in the block is missing a signal as a result of crossing domains. Suppose I have a low-frequency system clock, and a signal whose nature is that it rises for only one clock cycle. If the clock in the domain of that signal is faster than the system clock of my block, I may miss the arrival of the signal. Therefore the signal will enter the synchronizer, where it will be sampled and transferred to the domain of my block.
My desire in the code I wrote above is to make sure that the signal is synchronous, and therefore depends on the clock provided to me, meaning that the rise of the signal will always occur at the rise of its clock.
Thanks again! It is not obvious at all that you dedicate your time to helping and mentoring young engineers.