In reply to ben@SystemVerilog.us:
Thank you for your answer!
I don’t quite understand why
@(posedge ckA) $rose(a) |->
@(posedge ckA) @(posedge ckB) ##1 !b;
produces “sample rose on ckA, then wait one ckB before asserting the statement”, and not “sample rose on ckA, wait posedge ckA. Then, at the next posedge of ckB, wait one more posedge of ckB before asserting the statement”. I would be grateful if you could elaborate.
As you say
@(posedge ckA) $rose(a) |->
does not produce a double ckA, I’ve been reading my waveforms all wrong and my problem lies elsewhere. The signal a rises at the clockedge of ckA and I suppose that because of the preponed sampling the $rose(a) does not fire before the next posedge. Although
@(posedge ckB) ##1 !b;
seems to produce a double ckB wait. The waveform below shows the assertion starting at the clock edge after I want it to. The green lines indicate what I want to happen. How can I move the start of the assertion?
ckA = ckRead, ckB = ckWrite, a = fifoEmpty, b=fifoFull
Produced by:
@(posedge ckA) $rose(a) |->
@(posedge ckB) ##1 !b;