[SV LRM 2017] It shall be illegal to declare class method as static lifetime,but code is compiled and simulated successfully?

SystemVerilog
,
1

As per SV LRM 2017, under 8.6

The lifetime of methods declared as part of a class type shall be automatic. It shall be illegal to declare a
class method with a static lifetime.

but when I compiled this, it did compiled and simulated successfully, am i missing something?

2

In reply to juhi_p:

Not sure how to interpret the statement in the LRM. But your code is legal in my opinion.

In fact in Section 8.10 of the LRM you will see an example of a class declaration with static function.

3

In reply to juhi_p:

I believe the restriction for class is ::


   function static void display_function();
4

In reply to juhi_p:

See “static task” vs. “task static” | Verification Academy and follow the mentioned links.

5

As per section 8.10 static methods of LRM ,

A static method is different from a task with static lifetime. The former refers to the lifetime of the method within the class, while the latter refers to the lifetime of the arguments and variables within the task.

class TwoTasks;
static task t1(); ... endtask // static class method with
// automatic variable lifetime
task static t2(); ... endtask // ILLEGAL: non-static class method with
// static variable lifetime
endclass

but again this works fine with 2 simulator and 1 simulator is giving warnings. still working fine with all simulators.

6

In reply to juhi_p:

Actually, 2 simulators produce a warning and two simulators let it pass through. I would say that anyone who writes task static is probably confused with static task.

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