In reply to stefaniemcg:
In reply to ben@SystemVerilog.us:
Regarding why:
The reason why i want to code the reception/transmission of bits in the interface, is two fold.
First, because as far as i understand this is the benefit of using interfaces: to encapsulate the functionality of send and receive of the protocol in the interface itself, not only a bundle of signals.
Second, cuz else i’d have to code it in every single slave module, or master module connected to that protocol bus. But if i code it in the interface then the code is centralized for all modules which use the interface and protocol. Future changes to the protocol are centralized in the interface code, and not distributed all over my design.
Q1. Would you agree?
If I understand you correctly, you want to so something like this demo example:
interface Mux2to1Interface;
logic [1:0] data_in; // 2-bit input data
logic select; // Selection signal
logic data_out; // Output data
always_comb begin
if (select == 1'b0)
data_out = data_in[0];
else
data_out = data_in[1];
end
endinterface
// Implement a 2-to-1 multiplexer using the interface
module Mux2to1 (Mux2to1Interface ifc, logic clk);
logic[1:0] data_out_r;
logic[1:0] data_in_r;
always @(posedge clk) data_in_r <= ifc.data_in;
always @(posedge clk) data_out_r <= ifc.data_out;
endmodule
You now expect that the synthesis tools will merge into the Mux2to1 module the logic defined in the interface. I am not sure if this is acceptable by synthesis tools.
In SystemVerilog, interfaces are primarily used for design abstraction, code organization, and testbench modeling, and they are not typically used for synthesis. Interfaces provide a way to bundle signals together, define a set of methods (functions and tasks) that operate on those signals, and create hierarchical connections between modules. They are mainly used to improve code readability, reusability, and maintainability.
Synthesis tools typically do not support the direct synthesis of interfaces into hardware. Instead, synthesis is performed on modules or entities that use the interface. When you synthesize a module or entity that contains an interface, the synthesis tool will generate the appropriate hardware logic based on how the interface signals are used within that module/entity.
Because you want your code to be synthesizable, a better methodology would be to create separate modules for the master and slave protocols.
For assertions, you can create checkers or modules and bind them to the design units.
Also the reason why i ask, is cuz in the SV-LRM all examples use tasks to code functionality in the interfaces. I am used to code procBen Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
http://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf
or Links_to_papers_books - Google Docs
Getting started with verification with SystemVerilog
Free URL Shortener | Powered by Rebrandly logic, but seeing all examples were with tasks made me think twice.
That work is for verification, not for synthesis.
Regarding synthesizable code:
Now regarding synthesizable code, to my understanding both procedural logic (always…) and automatic tasks and functions are synthesizable (emphasizing the automatic).
Q2. Would you agree?
NO. Automatic tasks are not synthesizable; how do you dynamically create/destroy logic in silicon? That is why tasks are not synthesizable. Synthesis requires a template of acceptable constructs.