In reply to ben@SystemVerilog.us:
@Ben, hi
Regarding why:
The reason why i want to code the reception/transmission of bits in the interface, is two fold.
First, because as far as i understand this is the benefit of using interfaces: to encapsulate the functionality of send and receive of the protocol in the interface itself, not only a bundle of signals.
Second, cuz else i’d have to code it in every single slave module, or master module connected to that protocol bus. But if i code it in the interface then the code is centralized for all modules which use the interface and protocol. Future changes to the protocol are centralized in the interface code, and not distributed all over my design.
Q1. Would you agree?
Also the reason why i ask, is cuz in the SV-LRM all examples use tasks to code functionality in the interfaces. I am used to code procedural logic, but seeing all examples were with tasks made me think twise.
Regarding synthesizable code:
Now regarding synthesizable code, to my understanding both procedural logic (always…) and automatic tasks and functions are synthesizable (emphasizing the automatic).
Q2. Would you agree?
Thank you for your help.
Let me know your comments,