I’m coding the functionality of rx and tx of an interface in the interface it self.
This interface needs to be synthesizable.
[Ben] Why are you coding a synthesizable model of a RX/TX design in interface? SHouldn’t it be in a module?
Getting back to your question, if you want it in an interface, then procedural logic (always_ff, always_comb, etc) is the only way to go since tasks are typically dynamic, though you can declare them as static. It has been a long time since I used a synthesis tool, but I don’t believe that tasks are allowed.
Based on your requirements.
In VLSI industry, most important part is to extract the info/features from spec sheet. In other word, unserstand your design requirement first.
If requirement regarding send/receive packet or configuring the interface (High-level abstraction) than better to follow task/function.Because they have ability to code in simpler and more effective manner.
[Ben] I would use assertions, possibly with support logic, instead of tasks.
Ben Cohen
Ben@systemverilog.us
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