parameter ACTIVE_STATE 1
parameter IDLE_STATE 0
parameter LP_STATE 2
bit [2:0] fsm_state;
bit [5:0] outstanding_req
whenever fsm_state== ACTIVE_STATE 21 clock cycles and
outstanding_req==1 for 48 then fsm_state should move to IDLE_STATE in anywhere between 1-5 cycles…
Triggering condition is: fsm_state==ACTIVE_STATE for 21 cycles and outstanding_req==1 for 48 cycles continuously…
Any suggestions here??? I’m not sure how to write triggering condition
In reply to anirudh2:
If the trigger is for a testbench, then You can use an assertion with a sequence_match_item to cause the trigger. If it is for RTL, then you have to maintain the counters and the conditions under which they are incremented. Below is untested code, but it should give you guidance.
int count_state, count_req;
bit lock;
bit in_idle;
function void trigger_idle();
in_idle <= 1;
endfunction
ap_fsm2idle: assert property(fsm_state== ACTIVE_STATE[*21] and outstanding_req==1[*48]) |->
##[1:5] fsm_state == IDLE_STATE ##0 (1, trigger_idle());
always_ff @( clock ) begin : fms2idle
if(lock==0) begin : lockis0
if(fsm_state== ACTIVE_STATE && outstanding_req==1) begin
lock<=1;
count_state <=1;
count_req <= 1;
in_idle <= 0;
end
end : lockis0
// lock is 1
else if(fsm_state== ACTIVE_STATE && outstanding_req==1 && count_state !=21 ) begin // // lock==1
count_state <= count_state + 1;
count_req <= count_req + 1;
end
else if(outstanding_req==1 && count_state ==21 && count_req != 48) count_req <= count_req + 1;
else if(outstanding_req==1 && count_req != 48) count_req <= count_req + 1;
else if(count_req == 48) begin
in_idle <= 1;
lock <= 0;
end
else lock <= 0;
end