SV Constraint :: Address must be aligned to the size of the transfer

SystemVerilog
, ,
4

Thank you both Dave and Kranthi.
@dave_59 a question regarding above foreach constraint

foreach( axaddr[i] )
 {
     if( i inside { [0:(axsize-1)] } ) // confusion here                
    {
         axaddr[i] == 0; 
     }  
  }

[Q] If axsize is chosen as 0 , would there be any constraint on axaddr ?
Since (axsize-1) would be -1 shouldn’t there be a warning/error message ?
( as the range for inside operator must be [low:high] )