SV checker implementation

SystemVerilog
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1

Hi,

I want to implement a checker to verify something like the below logic in the design. I’m yet to figure out the clock and other signals required for this design. But just want to know what is the best way to validate this - assertion or an UVM class-based task?

R = (term-inductor)∗(code+legs)
loop=(R/(term_loop-inductor))-legs

Thanks

2

In reply to nimitz_class:

Very weak requirements!
Assertions are good. If the problem is too complex or needs to be in a class, you can use tasks as explained in my paper:

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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